/**
 * @file    gt9881_uart.h
 * @author  Giantec-Semi ATE
 * @brief   CMSIS GT98xx Device Peripheral Access Layer Header File
 * @version 0.1
 * 
 * @copyright Copyright (c) 2021 Giantec-Semi
 * 
 */

#ifndef GT98XX_DEVICE_GT9881_UART_H_
#define GT98XX_DEVICE_GT9881_UART_H_

#ifdef __cplusplus
  extern "C" {
#endif /* __cplusplus */

#include "gt9881.h"

/**
 * @addtogroup Peripheral_Registers_Structures
 * @{
 */
/**
 * @struct UartTypedef
 * @brief  UART registers structure definition
 */
typedef struct tagUartTypedef {
  __IO uint32_t RBR_THR_DLL;        ///< Receive Buff register/Transmit Holding Register/Divisor Latch (LOW)
  __IO uint32_t DLH_IER;            ///< Divisor Latch (High)/Interrupt Enable Register
  __IO uint32_t IIR;                ///< Interrupt Identification Register
  __IO uint32_t LCR;                ///< Line Control Register
  __IO uint32_t MCR;                ///< Modem Control Register
  __IO uint32_t LSR;                ///< Line Status Register
  __IO uint32_t MSR;                ///< Modem Status Register
  __IO uint32_t SCR;                ///< Scratchpad Register
       uint32_t RESERVED0[20];      ///< Reserved
  __IO uint32_t FAR;                ///< FIFO Access Register
  __IO uint32_t TFR;                ///< Transmit FIFO Read
  __IO uint32_t RFW;                ///< Receive FIFO Write
  __IO uint32_t USR;                ///< UART Status Register
       uint32_t RESERVED1[29];      ///< Reserved
  __IO uint32_t CPR;                ///< Component Parameter Register
  __IO uint32_t UCV;                ///< UART Component Version
  __IO uint32_t CTR;                ///< Component Type Register
} UartTypedef;
/** @} Peripheral_Registers_Structures */

/**
 * @addtogroup Peripheral_Memory_Map
 * @{
 */
#define UART_BASE                   (PERIPH_BASE + 0x4000UL)    ///< UART base address
/** @} Peripheral_Memory_Map */

/**
 * @addtogroup Peripheral_Declaration
 * @{
 */
#define UART                        ((UartTypedef*)UART_BASE)   ///< UART operator
/** @} Peripheral_Declaration */

/**
 * @defgroup UART_Bitmap UART Bitmap
 * @ingroup  Peripheral_Registers_Bits_Definition
 * @brief    Bitmap of UART registers
 * @{
 */

/******************* Bits definition of RBR *******************/
#define UART_RBR_Pos                            (0U)    ///< Position of UART_RBR
#define UART_RBR_Msk                            (0xFFUL << UART_RBR_Pos)    ///< Bitmask of UART_RBR
/**
 * @def   UART_RBR
 * @brief Data byte received on the serial input port in UART mode, or the serial infrared input in infrared mode
 */
#define UART_RBR                                UART_RBR_Msk

/******************* Bits definition of THR *******************/
#define UART_THR_Pos                            (0U)    ///< Position of UART_THR
#define UART_THR_Msk                            (0xFFUL << UART_THR_Pos)    ///< Bitmask of UART_THR
/**
 * @def   UART_THR
 * @brief Data to be transmitted on the serial output port in UART mode or the serial infrared output in infrared mode
 */
#define UART_THR                                UART_THR_Msk

/******************* Bits definition of DLL *******************/
#define UART_DLL_Pos                            (0U)    ///< Position of UART_DLL
#define UART_DLL_Msk                            (0xFFUL << UART_DLL_Pos)    ///< Bitmask of UART_DLL
/**
 * @def   UART_DLL
 * @brief Lower 8 bits of a 16-bit, read/write, Divisor Latch register
 */
#define UART_DLL                                UART_DLL_Msk

/******************* Bits definition of DLH *******************/
#define UART_DLH_Pos                            (0U)    ///< Position of UART_DLH
#define UART_DLH_Msk                            (0xFFUL << UART_DLH_Pos)    ///< Bitmask of UART_DLH
/**
 * @def   UART_DLH
 * @brief Upper 8-bits of a 16-bit, read/write, Divisor Latch register
 */
#define UART_DLH                                UART_DLH_Msk

/************************* Bits definition of IER *************************/
#define UART_IER_ERBFI_Pos                      (0U)    ///< Position of UART_IER_ERBFI
#define UART_IER_ERBFI_Msk                      (0x1UL << UART_IER_ERBFI_Pos)   ///< Bitmask of UART_IER_ERBFI
/**
 * @def   UART_IER_ERBFI
 * @brief Enable/disable received data available interrupt
 * <pre>
 * @a 1'b0 : Disable
 * @a 1'b1 : Enable
 * </pre>
 */
#define UART_IER_ERBFI                          UART_IER_ERBFI_Msk

#define UART_IER_ETBEI_Pos                      (1U)    ///< Position of UART_IER_ETBEI
#define UART_IER_ETBEI_Msk                      (0x1UL << UART_IER_ETBEI_Pos)   ///< Bitmask of UART_IER_ETBEI
/**
 * @def   UART_IER_ETBEI
 * @brief Enable/disable transmit holding register empty Interrupt
 * <pre>
 * @a 1'b0 : Disable
 * @a 1'b1 : Enable
 * </pre>
 */
#define UART_IER_ETBEI                          UART_IER_ETBEI_Msk

#define UART_IER_ELSI_Pos                       (2U)    ///< Position of UART_IER_ELSI
#define UART_IER_ELSI_Msk                       (0x1UL << UART_IER_ELSI_Pos)    ///< Bitmask of UART_IER_ELSI
/**
 * @def   UART_IER_ELSI
 * @brief Enable/disable receiver line status interrupt
 * <pre>
 * @a 1'b0 : Disable
 * @a 1'b1 : Enable
 * </pre>
 */
#define UART_IER_ELSI                           UART_IER_ELSI_Msk

#define UART_IER_EDSSI_Pos                      (3U)    ///< Position of UART_IER_EDSSI
#define UART_IER_EDSSI_Msk                      (0x1UL << UART_IER_EDSSI_Pos)   ///< Bitmask of UART_IER_EDSSI
/**
 * @def   UART_IER_EDSSI
 * @brief Enable/disable modem status interrupt
 * <pre>
 * @a 1'b0 : Disable
 * @a 1'b1 : Enable
 * </pre>
 */
#define UART_IER_EDSSI                          UART_IER_EDSSI_Msk

#define UART_IER_PTIME_Pos                      (7U)    ///< Position of UART_IER_PTIME
#define UART_IER_PTIME_Msk                      (0x1UL << UART_IER_PTIME_Pos)   ///< Bitmask of UART_IER_PTIME
/**
 * @def   UART_IER_PTIME
 * @brief Enable/disable THRE interrupt
 * <pre>
 * @a 1'b0 : Disable
 * @a 1'b1 : Enable
 * </pre>
 */
#define UART_IER_PTIME                          UART_IER_PTIME_Msk

/************************* Bits definition of IIR *************************/
#define UART_IIR_INTID_Pos                      (0U)    ///< Position of UART_IIR_INTID
#define UART_IIR_INTID_Msk                      (0xFUL << UART_IIR_INTID_Pos)   ///< Bitmask of UART_IIR_INTID
/**
 * @def   UART_IIR_INTID
 * @brief Interrupt ID. This indicates the highest priority pending interrupt
 * <pre>
 * @a 4'b0000 : modem status
 * @a 4'b0001 : no interrupt pending
 * @a 4'b0010 : THR empt
 * @a 4'b0100 : received data available
 * @a 4'b0110 : receiver line statue
 * @a 4'b0111 : busy detect
 * @a 4'b1100 : character timeout
 * </pre>
 */
#define UART_IIR_INTID                          UART_IIR_INTID_Msk

#define UART_IIR_FIFO_EN_Pos                    (6U)    ///< Position of UART_IIR_FIFO_EN
#define UART_IIR_FIFO_EN_Msk                    (0x3UL << UART_IIR_FIFO_EN_Pos) ///< Bitmask of UART_IIR_FIFO_EN
/**
 * @def   UART_IIR_FIFO_EN
 * @brief Enable/disable FIFOs
 * <pre>
 * @a 2'b00 : Disable
 * @a 2'b11 : Enable
 * </pre>
 */
#define UART_IIR_FIFO_EN                        UART_IIR_FIFO_EN_Msk

/*********************** Bits definition of LCR ***********************/
#define UART_LCR_DLS_Pos                        (0U)    ///< Position of UART_LCR_DLS
#define UART_LCR_DLS_Msk                        (0x3UL << UART_LCR_DLS_Pos) ///< Bitmask of UART_LCR_DLS
/**
 * @def   UART_LCR_DLS
 * @brief Data length select
 * <pre>
 * @a 2'b00 : 5 bits
 * @a 2'b01 : 6 bits
 * @a 2'b10 : 7 bits
 * @a 2'b11 : 8 bits
 * </pre>
 */
#define UART_LCR_DLS                            UART_LCR_DLS_Msk

#define UART_LCR_STOP_Pos                       (2U)    ///< Position of UART_LCR_STOP
#define UART_LCR_STOP_Msk                       (0x1UL << UART_LCR_STOP_Pos)    ///< Bitmask of UART_LCR_STOP
/**
 * @def   UART_LCR_STOP
 * @brief Number of stop bits.
 * <pre>
 * @a 1'b0 : 1 bit stop bits
 * @a 1'b1 : 1.5 bit stop bits (when DLS (LCR[1:0]) is 0)
 *           or 2 stop bits (when DLS (LCR[1:0]) is 1)
 * </pre>
 */
#define UART_LCR_STOP                           UART_LCR_STOP_Msk

#define UART_LCR_PEN_Pos                        (3U)    ///< Position of UART_LCR_PEN
#define UART_LCR_PEN_Msk                        (0x1UL << UART_LCR_PEN_Pos) ///< Bitmask of UART_LCR_PEN
/**
 * @def   UART_LCR_PEN
 * @brief Enable/disable parity
 * <pre>
 * @a 1'b0 : Disable
 * @a 1'b1 : Enable
 * </pre>
 */
#define UART_LCR_PEN                            UART_LCR_PEN_Msk

#define UART_LCR_EPS_Pos                        (4U)    ///< Position of UART_LCR_EPS
#define UART_LCR_EPS_Msk                        (0x1UL << UART_LCR_EPS_Pos) ///< Bitmask of UART_LCR_EPS
/**
 * @def   UART_LCR_EPS
 * @brief Even parity select
 * <pre>
 * @a 1'b0 : An odd number of logic 1s is transmitted or checked.
 * @a 1'b1 : An even number of logic 1s is transmitted or checked.
 * </pre>
 */
#define UART_LCR_EPS                            UART_LCR_EPS_Msk

#define UART_LCR_STICK_PARITY_Pos               (5U)    ///< Position of UART_LCR_STICK_PARITY
#define UART_LCR_STICK_PARITY_Msk               (0x1UL << UART_LCR_STICK_PARITY_Pos)    ///< Bitmask of UART_LCR_STICK_PARITY
/**
 * @def   UART_LCR_STICK_PARITY
 * @brief Force parity value.
 * <pre>
 * @a 1'b0 : Stick Parity is disabled.
 * @a 1'b1 : PEN: 1 EPS: 1 Parity: 1 : The parity bit is transmitted and checked as logic 0
 *           PEN: 1 EPS: 0 Parity: 1 : The parity bit is transmitted and checked as logic 1
 * </pre>
 */
#define UART_LCR_STICK_PARITY                   UART_LCR_STICK_PARITY_Msk

#define UART_LCR_BREAK_Pos                      (6U)    ///< Position of UART_LCR_BREAK
#define UART_LCR_BREAK_Msk                      (0x1UL << UART_LCR_BREAK_Pos)   ///< Bitmask of UART_LCR_BREAK
/**
 * @def   UART_LCR_BREAK
 * @brief Break control bit
 * <pre>
 * @a 1'b0 : An odd number of logic 1s is transmitted or checked.
 * @a 1'b1 : PEN: 1 EPS: 1 : The parity bit is transmitted and checked as logic 0.
 * </pre>
 */
#define UART_LCR_BREAK                          UART_LCR_BREAK_Msk

#define UART_LCR_DLAB_Pos                       (7U)    ///< Position of UART_LCR_DLAB
#define UART_LCR_DLAB_Msk                       (0x1UL << UART_LCR_DLAB_Pos)    ///< Bitmask of UART_LCR_DLAB
/**
 * @def   UART_LCR_DLAB
 * @brief Enable reading and writing of the Divisor Latch register
 */
#define UART_LCR_DLAB                           UART_LCR_DLAB_Msk

/*********************** Bits definition of MCR ***********************/
#define UART_MCR_DTR_Pos                        (0U)    ///< Position of UART_MCR_DTR
#define UART_MCR_DTR_Msk                        (0x1UL << UART_MCR_DTR_Pos) ///< Bitmask of UART_MCR_DTR
/**
 * @def   UART_MCR_DTR
 * @brief Directly control the Request to Send (rts_n) output.
 * <pre>
 * @a 1'b0 : Dtr_n de-asserted (logic 1)
 * @a 1'b1 : Dtr_n asserted (logic 0)
 * </pre>
 */
#define UART_MCR_DTR                            UART_MCR_DTR_Msk

#define UART_MCR_RTS_Pos                        (1U)    ///< Position of UART_MCR_RTS
#define UART_MCR_RTS_Msk                        (0x1UL << UART_MCR_RTS_Pos) ///< Bitmask of UART_MCR_RTS
/**
 * @def   UART_MCR_RTS
 * @brief Directly control the Data Terminal Ready (dtr_n) output.
 */
#define UART_MCR_RTS                            UART_MCR_RTS_Msk

#define UART_MCR_OUT1_Pos                       (2U)    ///< Position of UART_MCR_OUT1
#define UART_MCR_OUT1_Msk                       (0x1UL << UART_MCR_OUT1_Pos)    ///< Bitmask of UART_MCR_OUT1
/**
 * @def   UART_MCR_OUT1
 * @brief Directly control the user-designated Output1 (out1_n) output.
 * <pre>
 * @a 1'b0 : Out1_n de-asserted (logic 1)
 * @a 1'b1 : Out1_n asserted (logic 0)
 * </pre>
 */
#define UART_MCR_OUT1                           UART_MCR_OUT1_Msk

#define UART_MCR_OUT2_Pos                       (3U)    ///< Position of UART_MCR_OUT2
#define UART_MCR_OUT2_Msk                       (0x1UL << UART_MCR_OUT2_Pos)    ///< Bitmask of UART_MCR_OUT2
/**
 * @def   UART_MCR_OUT2
 * @brief Directly control the user-designated Output2 (out2_n) output.
 * <pre>
 * @a 1'b0 : Out2_n de-asserted (logic 1)
 * @a 1'b1 : Out2_n asserted (logic 0)
 * </pre>
 */
#define UART_MCR_OUT2                           UART_MCR_OUT2_Msk

#define UART_MCR_LOOPBACK_Pos                   (4U)    ///< Position of UART_MCR_LOOPBACK
#define UART_MCR_LOOPBACK_Msk                   (0x1UL << UART_MCR_LOOPBACK_Pos)    ///< Bitmask of UART_MCR_LOOPBACK
/**
 * @def   UART_MCR_LOOPBACK
 * @brief Put the UART into a diagnostic mode for test purposes.
 * <pre>
 * @a 1'b0 : Out1_n de-asserted (logic 1)
 * @a 1'b1 : Out1_n asserted (logic 0)
 * </pre>
 */
#define UART_MCR_LOOPBACK                       UART_MCR_LOOPBACK_Msk

#define UART_MCR_AFCE_Pos                       (5U)    ///< Position of UART_MCR_AFCE
#define UART_MCR_AFCE_Msk                       (0x1UL << UART_MCR_AFCE_Pos)    ///< Bitmask of UART_MCR_AFCE
/**
 * @def   UART_MCR_AFCE
 * @brief Enable/disable Flow Control Mode
 * <pre>
 * @a 1'b0 : Disable
 * @a 1'b1 : Enable
 * </pre>
 */
#define UART_MCR_AFCE                           UART_MCR_AFCE_Msk

#define UART_MCR_SIRE_Pos                       (6U)    ///< Position of UART_MCR_SIRE
#define UART_MCR_SIRE_Msk                       (0x1UL << UART_MCR_SIRE_Pos)    ///< Bitmask of UART_MCR_SIRE
/**
 * @def   UART_MCR_SIRE
 * @brief Enable/disable SIR Mode
 */
#define UART_MCR_SIRE                           UART_MCR_SIRE_Msk

/********************** Bits definition of LSR **********************/
#define UART_LSR_DR_Pos                         (0U)    ///< Position of UART_LSR_DR
#define UART_LSR_DR_Msk                         (0x1UL << UART_LSR_DR_Pos)  ///< Bitmask of UART_LSR_DR
/**
 * @def   UART_LSR_DR
 * @brief Indicate that the receiver contains at least one character in the RBR or the receiver FIFO.
 * <pre>
 * @a 1'b0 : No data ready
 * @a 1'b1 : Data ready
 * </pre>
 */
#define UART_LSR_DR                             UART_LSR_DR_Msk

#define UART_LSR_OE_Pos                         (1U)    ///< Position of UART_LSR_OE
#define UART_LSR_OE_Msk                         (0x1UL << UART_LSR_OE_Pos)  ///< Bitmask of UART_LSR_OE
/**
 * @def   UART_LSR_OE
 * @brief Indicate the occurrence of an overrun error
 * <pre>
 * @a 1'b0 : No overrun error
 * @a 1'b1 : Overrun error
 * </pre>
 */
#define UART_LSR_OE                             UART_LSR_OE_Msk

#define UART_LSR_PE_Pos                         (2U)    ///< Position of UART_LSR_PE
#define UART_LSR_PE_Msk                         (0x1UL << UART_LSR_PE_Pos)  ///< Bitmask of UART_LSR_PE
/**
 * @def   UART_LSR_PE
 * @brief Indicate the occurrence of a parity error in the receiver
 * <pre>
 * @a 1'b0 : No parity error
 * @a 1'b1 : Parity error
 * </pre>
 */
#define UART_LSR_PE                             UART_LSR_PE_Msk

#define UART_LSR_FE_Pos                         (3U)    ///< Position of UART_LSR_FE
#define UART_LSR_FE_Msk                         (0x1UL << UART_LSR_FE_Pos)  ///< Bitmask of UART_LSR_FE
/**
 * @def   UART_LSR_FE
 * @brief Indicate the occurrence of a framing error
 * <pre>
 * @a 1'b0 : No farming error
 * @a 1'b1 : Framing error Reading the LSR clears the FE bit.
 * </pre>
 */
#define UART_LSR_FE                             UART_LSR_FE_Msk

#define UART_LSR_BI_Pos                         (4U)    ///< Position of UART_LSR_BI
#define UART_LSR_BI_Msk                         (0x1UL << UART_LSR_BI_Pos)  ///< Bitmask of UART_LSR_BI
/**
 * @def   UART_LSR_BI
 * @brief Indicate the detection of a break sequence on the serial input data.
 */
#define UART_LSR_BI                             UART_LSR_BI_Msk

#define UART_LSR_THRE_Pos                       (5U)    ///< Position of UART_LSR_THRE
#define UART_LSR_THRE_Msk                       (0x1UL << UART_LSR_THRE_Pos)    ///< Bitmask of UART_LSR_THRE
/**
 * @def   UART_LSR_THRE
 * @brief Indicates the THR or TX FIFO is empty.
 */
#define UART_LSR_THRE                           UART_LSR_THRE_Msk

#define UART_LSR_TEMT_Pos                       (6U)    ///< Position of UART_LSR_TEMT
#define UART_LSR_TEMT_Msk                       (0x1UL << UART_LSR_TEMT_Pos)    ///< Bitmask of UART_LSR_TEMT
/**
 * @def   UART_LSR_TEMT
 * @brief Transmitter empty bit.
 */
#define UART_LSR_TEMT                           UART_LSR_TEMT_Msk

#define UART_LSR_RFE_Pos                        (7U)    ///< Position of UART_LSR_RFE
#define UART_LSR_RFE_Msk                        (0x1UL << UART_LSR_RFE_Pos) ///< Bitmask of UART_LSR_RFE
/**
 * @def   UART_LSR_RFE
 * @brief Indicate if there is at least one parity error, framing error, or break indication in the FIFO.
 * <pre>
 * @a 1'b0 : No error in RX FIFO
 * @a 1'b1 : Error in RX FIFO.
 * Only relevant when FCR[0] set to 1
 * </pre>
 */
#define UART_LSR_RFE                            UART_LSR_RFE_Msk

#define UART_LSR_ADDR_RCVD_Pos                  (8U)    ///< Position of UART_LSR_ADDR_RCVD
#define UART_LSR_ADDR_RCVD_Msk                  (0x1UL << UART_LSR_ADDR_RCVD_Pos)   ///< Bitmask of UART_LSR_ADDR_RCVD
/**
 * @def   UART_LSR_ADDR_RCVD
 * @brief Indicate that the 9th bit of the receive data is set to 1/indicate whether the incoming character is an address or data
 * <pre>
 * @a 1'b0 : Indicates that the character is an address
 * @a 1'b1 : Indicates that the character is data.
 * </pre>
 */
#define UART_LSR_ADDR_RCVD                      UART_LSR_ADDR_RCVD_Msk

/************************ Bits definition of MSR ************************/
#define UART_MSR_DCTS_Pos                       (0U)    ///< Position of UART_MSR_DCTS
#define UART_MSR_DCTS_Msk                       (0x1UL << UART_MSR_DCTS_Pos)    ///< Bitmask of UART_MSR_DCTS
/**
 * @def   UART_MSR_DCTS
 * @brief Indicate the modem control line cts_n has changed since the last time the MSR was read
 * <pre>
 * @a 1'b0 : No change on cts_n since last read of MSR
 * @a 1'b1 : Change on cts_n since last read of MSR
 * </pre>
 */
#define UART_MSR_DCTS                           UART_MSR_DCTS_Msk

#define UART_MSR_DDSR_Pos                       (1U)    ///< Position of UART_MSR_DDSR
#define UART_MSR_DDSR_Msk                       (0x1UL << UART_MSR_DDSR_Pos)    ///< Bitmask of UART_MSR_DDSR
/**
 * @def   UART_MSR_DDSR
 * @brief Indicate the modem control line dsr_n has changed since the last time the MSR was read
 * <pre>
 * @a 1'b0 : No change on dsr_n since last read of MSR
 * @a 1'b1 : Change on dsr_n since last read of MSR
 * </pre>
 */
#define UART_MSR_DDSR                           UART_MSR_DDSR_Msk

#define UART_MSR_TERI_Pos                       (2U)    ///< Position of UART_MSR_TERI
#define UART_MSR_TERI_Msk                       (0x1UL << UART_MSR_TERI_Pos)    ///< Bitmask of UART_MSR_TERI
/**
 * @def   UART_MSR_TERI
 * @brief Indicate that a change on the input ri_n has occurred since the last time the MSR was read.
 * <pre>
 * @a 1'b0 : No change on ri_n since last read of MSR
 * @a 1'b1 : Change on ri_n since last read of MSR
 * </pre>
 */
#define UART_MSR_TERI                           UART_MSR_TERI_Msk

#define UART_MSR_DDCD_Pos                       (3U)    ///< Position of UART_MSR_DDCD
#define UART_MSR_DDCD_Msk                       (0x1UL << UART_MSR_DDCD_Pos)    ///< Bitmask of UART_MSR_DDCD
/**
 * @def   UART_MSR_DDCD
 * @brief Indicate that a change on the input ri_n has changed since the last time the MSR was read.
 * <pre>
 * @a 1'b0 : No change on dcd_n since last read of MSR
 * @a 1'b1 : Change on dcd_n since last read of MSR
 * </pre>
 */
#define UART_MSR_DDCD                           UART_MSR_DDCD_Msk

#define UART_MSR_CTS_Pos                        (4U)    ///< Position of UART_MSR_CTS
#define UART_MSR_CTS_Msk                        (0x1UL << UART_MSR_CTS_Pos) ///< Bitmask of UART_MSR_CTS
/**
 * @def   UART_MSR_CTS
 * @brief Indicate the current state of the modem control line cts_n
 * <pre>
 * @a 1'b0 : Cts_n input is de-asserted (logic 1)
 * @a 1'b1 : Cts_n input is asserted (logic 0)
 * </pre>
 */
#define UART_MSR_CTS                            UART_MSR_CTS_Msk

#define UART_MSR_DSR_Pos                        (5U)    ///< Position of UART_MSR_DSR
#define UART_MSR_DSR_Msk                        (0x1UL << UART_MSR_DSR_Pos) ///< Bitmask of UART_MSR_DSR
/**
 * @def   UART_MSR_DSR
 * @brief Indicate the current state of the modem control line dsr_n
 * <pre>
 * @a 1'b0 : Dsr_n input is de-asserted (logic 1)
 * @a 1'b1 : Dsr_n input is asserted (logic 0)
 * </pre>
 */
#define UART_MSR_DSR                            UART_MSR_DSR_Msk

#define UART_MSR_RI_Pos                         (6U)    ///< Position of UART_MSR_RI
#define UART_MSR_RI_Msk                         (0x1UL << UART_MSR_RI_Pos)  ///< Bitmask of UART_MSR_RI
/**
 * @def   UART_MSR_RI
 * @brief Indicate the current state of the modem control line ri_n
 * <pre>
 * @a 1'b0 : Ri_n input is de-asserted (logic 1)
 * @a 1'b1 : Ri_n input is asserted (logic 0)
 * </pre>
 */
#define UART_MSR_RI                             UART_MSR_RI_Msk

#define UART_MSR_DCD_Pos                        (7U)    ///< Position of UART_MSR_DCD
#define UART_MSR_DCD_Msk                        (0x1UL << UART_MSR_DCD_Pos) ///< Bitmask of UART_MSR_DCD
/**
 * @def   UART_MSR_DCD
 * @brief Indicate the current state of the modem control line dcd_n
 * <pre>
 * @a 1'b0 : Dcd_n input is de-asserted (logic 1)
 * @a 1'b1 : Dcd_n input is asserted (logic 0)
 * </pre>
 */
#define UART_MSR_DCD                            UART_MSR_DCD_Msk

/******************* Bits definition of SCR *******************/
#define UART_SCR_Pos                            (0U)    ///< Position of UART_SCR
#define UART_SCR_Msk                            (0xFFUL << UART_SCR_Pos)    ///< Bitmask of UART_SCR
/**
 * @def   UART_SCR
 * @brief Use as a temporary storage space.
 */
#define UART_SCR                                UART_SCR_Msk

/********************** Bits definition of FAR **********************/
#define UART_FAR_FIFO_EN_Pos                         (0U)    ///< Position of UART_FAR_FIFO_EN
#define UART_FAR_FIFO_EN_Msk                         (0x1UL << UART_FAR_FIFO_EN_Pos)  ///< Bitmask of UART_FAR_FIFO_EN
/**
 * @def   UART_FAR_FIFO_EN
 * @brief Enable/disable a FIFO access mode for testing
 * <pre>
 * @a 1'b0 : FIFO access mode disabled
 * @a 1'b1 : FIFO access mode enabled
 * </pre>
 */
#define UART_FAR_FIFO_EN                             UART_FAR_FIFO_EN_Msk

/******************* Bits definition of TFR *******************/
#define UART_TFR_Pos                            (0U)    ///< Position of UART_TFR
#define UART_TFR_Msk                            (0xFFUL << UART_TFR_Pos)    ///< Bitmask of UART_TFR
/**
 * @def   UART_TFR
 * @brief Transmit FIFO Read
 */
#define UART_TFR                                UART_TFR_Msk

/************************ Bits definition of RFW ************************/
#define UART_RFW_RFWD_Pos                       (0U)    ///< Position of UART_RFW_RFWD
#define UART_RFW_RFWD_Msk                       (0xFUL << UART_RFW_RFWD_Pos)    ///< Bitmask of UART_RFW_RFWD
/**
 * @def   UART_RFW_RFWD
 * @brief Receive FIFO write data
 * <pre>
 * Only valid when FIFO access mode is enabled
 * </pre>
 */
#define UART_RFW_RFWD                           UART_RFW_RFWD_Msk

#define UART_RFW_RFPE_Pos                       (8U)    ///< Position of UART_RFW_RFPE
#define UART_RFW_RFPE_Msk                       (0x1UL << UART_RFW_RFPE_Pos)    ///< Bitmask of UART_RFW_RFPE
/**
 * @def   UART_RFW_RFPE
 * @brief Receive FIFO parity error.
 * <pre>
 * Only valid when FIFO access mode is enabled
 * </pre>
 */
#define UART_RFW_RFPE                           UART_RFW_RFPE_Msk

#define UART_RFW_RFFE_Pos                       (9U)    ///< Position of UART_RFW_RFFE
#define UART_RFW_RFFE_Msk                       (0x1UL << UART_RFW_RFFE_Pos)    ///< Bitmask of UART_RFW_RFFE
/**
 * @def   UART_RFW_RFFE
 * @brief Receive FIFO farming error
 * <pre>
 * Only valid when FIFO access mode is enabled
 * </pre>
 */
#define UART_RFW_RFFE                           UART_RFW_RFFE_Msk

/************************ Bits definition of USR ************************/
#define UART_USR_TFNF_Pos                       (1U)    ///< Position of UART_USR_TFNF
#define UART_USR_TFNF_Msk                       (0x1UL << UART_USR_TFNF_Pos)    ///< Bitmask of UART_USR_TFNF
/**
 * @def   UART_USR_TFNF
 * @brief Indicate the transmit FIFO in not full
 * <pre>
 * @a 1'b0 : Transmit FIFO is full
 * @a 1'b1 : Transmit FIFO is not full
 * </pre>
 */
#define UART_USR_TFNF                           UART_USR_TFNF_Msk

#define UART_USR_TFE_Pos                        (2U)    ///< Position of UART_USR_TFE
#define UART_USR_TFE_Msk                        (0x1UL << UART_USR_TFE_Pos) ///< Bitmask of UART_USR_TFE
/**
 * @def   UART_USR_TFE
 * @brief Indicate the transmit FIFO is completely empty
 * <pre>
 * @a 1'b0 : Transmit FIFO is not empty
 * @a 1'b1 : Transmit FIFO is empty
 * </pre>
 */
#define UART_USR_TFE                            UART_USR_TFE_Msk

#define UART_USR_RFNE_Pos                       (3U)    ///< Position of UART_USR_RFNE
#define UART_USR_RFNE_Msk                       (0x1UL << UART_USR_RFNE_Pos)    ///< Bitmask of UART_USR_RFNE
/**
 * @def   UART_USR_RFNE
 * @brief Indicate the receive FIFO contains one or more entries.
 * <pre>
 * @a 1'b0 : Receive FIFO is empty
 * @a 1'b1 : Receive FIFO is not empty
 * </pre>
 */
#define UART_USR_RFNE                           UART_USR_RFNE_Msk

#define UART_USR_RFF_Pos                        (4U)    ///< Position of UART_USR_RFF
#define UART_USR_RFF_Msk                        (0x1UL << UART_USR_RFF_Pos) ///< Bitmask of UART_USR_RFF
/**
 * @def   UART_USR_RFF
 * @brief Indicate the receive FIFO is completely full.
 * <pre>
 * @a 1'b0 : Receive FIFO not full
 * @a 1'b1 : Receive FIFO full
 * </pre>
 */
#define UART_USR_RFF                            UART_USR_RFF_Msk

/********************************** Bits definition of CPR **********************************/
#define UART_CPR_APB_DATA_WIDTH_Pos             (0U)    ///< Position of UART_CPR_APB_DATA_WIDTH
#define UART_CPR_APB_DATA_WIDTH_Msk             (0x3UL << UART_CPR_APB_DATA_WIDTH_Pos)  ///< Bitmask of UART_CPR_APB_DATA_WIDTH
/**
 * @def   UART_CPR_APB_DATA_WIDTH
 * @brief Width of data
 * <pre>
 * @a 2'b00 : 8 bits
 * @a 2'b01 : 16 bits
 * @a 2'b10 : 32 bits
 * @a 2'b11 : reserved
 * </pre>
 */
#define UART_CPR_APB_DATA_WIDTH                 UART_CPR_APB_DATA_WIDTH_Msk

#define UART_CPR_AFCE_MODE_Pos                  (4U)    ///< Position of UART_CPR_AFCE_MODE
#define UART_CPR_AFCE_MODE_Msk                  (0x1UL << UART_CPR_AFCE_MODE_Pos)   ///< Bitmask of UART_CPR_AFCE_MODE
/**
 * @def   UART_CPR_AFCE_MODE
 * @brief If AFCE mode is on
 * <pre>
 * @a 1'b0 : FALSE
 * @a 1'b1 : TRUE
 * </pre>
 */
#define UART_CPR_AFCE_MODE                      UART_CPR_AFCE_MODE_Msk

#define UART_CPR_THRE_MODE_Pos                  (5U)    ///< Position of UART_CPR_THRE_MODE
#define UART_CPR_THRE_MODE_Msk                  (0x1UL << UART_CPR_THRE_MODE_Pos)   ///< Bitmask of UART_CPR_THRE_MODE
/**
 * @def   UART_CPR_THRE_MODE
 * @brief If THRE mode is on
 * <pre>
 * @a 1'b0 : FALSE
 * @a 1'b1 : TRUE
 * </pre>
 */
#define UART_CPR_THRE_MODE                      UART_CPR_THRE_MODE_Msk

#define UART_CPR_SIR_MODE_Pos                   (6U)    ///< Position of UART_CPR_SIR_MODE
#define UART_CPR_SIR_MODE_Msk                   (0x1UL << UART_CPR_SIR_MODE_Pos)    ///< Bitmask of UART_CPR_SIR_MODE
/**
 * @def   UART_CPR_SIR_MODE
 * @brief If SIR mode is on
 * <pre>
 * @a 1'b0 : FALSE
 * @a 1'b1 : TRUE
 * </pre>
 */
#define UART_CPR_SIR_MODE                       UART_CPR_SIR_MODE_Msk

#define UART_CPR_SIR_LP_MODE_Pos                (7U)    ///< Position of UART_CPR_SIR_LP_MODE
#define UART_CPR_SIR_LP_MODE_Msk                (0x1UL << UART_CPR_SIR_LP_MODE_Pos) ///< Bitmask of UART_CPR_SIR_LP_MODE
/**
 * @def   UART_CPR_SIR_LP_MODE
 * @brief If SIR_LP mode is on
 * <pre>
 * @a 1'b0 : FALSE
 * @a 1'b1 : TRUE
 * </pre>
 */
#define UART_CPR_SIR_LP_MODE                    UART_CPR_SIR_LP_MODE_Msk

#define UART_CPR_ADDITIONAL_FEAT_Pos            (8U)    ///< Position of UART_CPR_ADDITIONAL_FEAT
#define UART_CPR_ADDITIONAL_FEAT_Msk            (0x1UL << UART_CPR_ADDITIONAL_FEAT_Pos) ///< Bitmask of UART_CPR_ADDITIONAL_FEAT
/**
 * @def   UART_CPR_ADDITIONAL_FEAT
 * @brief If there is additional feat
 * <pre>
 * @a 1'b0 : FALSE
 * @a 1'b1 : TRUE
 * </pre>
 */
#define UART_CPR_ADDITIONAL_FEAT                UART_CPR_ADDITIONAL_FEAT_Msk

#define UART_CPR_FIFO_ACCESS_Pos                (9U)    ///< Position of UART_CPR_FIFO_ACCESS
#define UART_CPR_FIFO_ACCESS_Msk                (0x1UL << UART_CPR_FIFO_ACCESS_Pos) ///< Bitmask of UART_CPR_FIFO_ACCESS
/**
 * @def   UART_CPR_FIFO_ACCESS
 * @brief If the FIFO is accessable
 * <pre>
 * @a 1'b0 : FALSE
 * @a 1'b1 : TRUE
 * </pre>
 */
#define UART_CPR_FIFO_ACCESS                    UART_CPR_FIFO_ACCESS_Msk

#define UART_CPR_FIFO_STAT_Pos                  (10U)   ///< Position of UART_CPR_FIFO_STAT
#define UART_CPR_FIFO_STAT_Msk                  (0x1UL << UART_CPR_FIFO_STAT_Pos)   ///< Bitmask of UART_CPR_FIFO_STAT
/**
 * @def   UART_CPR_FIFO_STAT
 * @brief If the FIFO is started
 * <pre>
 * @a 1'b0 : FALSE
 * @a 1'b1 : TRUE
 * </pre>
 */
#define UART_CPR_FIFO_STAT                      UART_CPR_FIFO_STAT_Msk

#define UART_CPR_SHADOW_Pos                     (11U)   ///< Position of UART_CPR_SHADOW
#define UART_CPR_SHADOW_Msk                     (0x1UL << UART_CPR_SHADOW_Pos)  ///< Bitmask of UART_CPR_SHADOW
/**
 * @def   UART_CPR_SHADOW
 * @brief If there is shadow
 * <pre>
 * @a 1'b0 : FALSE
 * @a 1'b1 : TRUE
 * </pre>
 */
#define UART_CPR_SHADOW                         UART_CPR_SHADOW_Msk

#define UART_CPR_UART_ADD_ENCODED_PARAMS_Pos    (12U)   ///< Position of UART_CPR_UART_ADD_ENCODED_PARAMS
#define UART_CPR_UART_ADD_ENCODED_PARAMS_Msk    (0x1UL << UART_CPR_UART_ADD_ENCODED_PARAMS_Pos) ///< Bitmask of UART_CPR_UART_ADD_ENCODED_PARAMS
/**
 * @def   UART_CPR_UART_ADD_ENCODED_PARAMS
 * @brief If UART has added the encoded params
 * <pre>
 * @a 1'b0 : FALSE
 * @a 1'b1 : TRUE
 * </pre>
 */
#define UART_CPR_UART_ADD_ENCODED_PARAMS        UART_CPR_UART_ADD_ENCODED_PARAMS_Msk

#define UART_CPR_DMA_EXTRA_Pos                  (13U)   ///< Position of UART_CPR_DMA_EXTRA
#define UART_CPR_DMA_EXTRA_Msk                  (0x1UL << UART_CPR_DMA_EXTRA_Pos)   ///< Bitmask of UART_CPR_DMA_EXTRA
/**
 * @def   UART_CPR_DMA_EXTRA
 * @brief If DMA is in use
 * <pre>
 * @a 1'b0 : FALSE
 * @a 1'b1 : TRUE
 * </pre>
 */
#define UART_CPR_DMA_EXTRA                      UART_CPR_DMA_EXTRA_Msk

#define UART_CPR_FIFO_MODE_Pos                  (16U)   ///< Position of UART_CPR_FIFO_MODE
#define UART_CPR_FIFO_MODE_Msk                  (0xFFUL << UART_CPR_FIFO_MODE_Pos)  ///< Bitmask of UART_CPR_FIFO_MODE
/**
 * @def   UART_CPR_FIFO_MODE
 * @brief FIFO mode
 * <pre>
 * @a 8'h0x00~0x80 : 0~2048
 * @a 8'h0x81~0xFF : reserved
 * </pre>
 */
#define UART_CPR_FIFO_MODE                      UART_CPR_FIFO_MODE_Msk

/******************* Bits definition of UCR *******************/
#define UART_UCR_Pos                            (0U)    ///< Position of UART_UCR
#define UART_UCR_Msk                            (0xFFFFFFFFUL << UART_UCR_Pos)  ///< Bitmask of UART_UCR
/**
 * @def   UART_UCR
 * @brief ASCII value for each number in the version
 */
#define UART_UCR                                UART_UCR_Msk

/******************* Bits definition of CTR *******************/
#define UART_CTR_Pos                            (0U)    ///< Position of UART_CTR
#define UART_CTR_Msk                            (0xFFFFFFFFUL << UART_CTR_Pos)  ///< Bitmask of UART_CTR
/**
 * @def   UART_CTR
 * @brief contains the peripherals identification code
 */
#define UART_CTR                                UART_CTR_Msk

/** @} UART_Bitmap */

/**
 * @addtogroup Exported_Macros
 * @{
 */

/**
 * @def   IS_UART_INSTANCE
 * @brief Check if INSTANCE is UART instance
 */
#define IS_UART_INSTANCE(INSTANCE)              ((INSTANCE) == UART)

/** @} Exported_Macros */

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* GT98XX_DEVICE_GT9881_UART_H_ */
